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CPU Simulator
this entry is written twice, in full
- 1.in brief
3-stage pipelined CPU simulator
- 2.in general
Three stages, and every hazard between them.
- 3.in particular
A C++ CPU simulator with a 3-stage pipeline, hazard detection, and data forwarding.
- 1.in brief
a processor simulated in software, one stage at a time
- 2.in general
Three stages, and every way they can trip over each other.
- 3.in particular
A processor model with a three-stage pipeline, collision detection, and results passed straight back.
note
An OOP CPU model with a fetch/decode/execute pipeline, custom ISA, memory hierarchy with cache levels, hazard detection, branch prediction, and data forwarding to minimize stalls: three stages’ worth of machinery so that nothing has to wait a cycle.
note
A model of a processor that fetches, decodes and executes instructions in an overlapping sequence, with its own instruction set, layered memory, detection for when one instruction needs a result the previous one has not finished producing, guessing at which way a branch will go, and passing results straight backwards so that nothing has to sit and wait. Three stages’ worth of machinery, all of it there so nothing wastes a cycle.